1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to a low power memory controller placed on a two-layer printed circuit board (PCB) with a double data rate (DDR) DRAM, both of which are packaged with leads extending outward from the package and secured to pads on the PCB for a lower cost semiconductor memory system.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
There are numerous types of memories available in the marketplace. For example, large volumes of data can be stored in magnetic memory, such as a hard disk drive. Lesser quantities of data can be stored in memory arranged upon an integrated circuit, oftentimes referred to as “semiconductor memory.” Semiconductor memory is typically arranged closer to the core logic unit, or execution unit, than the hard disk drive and can be accessed much faster than the disk drive.
Common to semiconductor memory is an array of storage cells. Depending on the function of the semiconductor memory, each storage cell can have a significantly different architecture and function. For example, semiconductor memory can be volatile or non-volatile. Types of volatile memory include memory which must be periodically refreshed (DRAMs) or memory that will lose its programmed state if power is removed (SRAMs).
The differences between SRAMs and DRAMs are fairly significant. For example, each cell of SRAM includes latch and pass transistors. Conversely, each cell of DRAM involves simply one transistor. While DRAMs are denser than SRAMs, DRAMs require additional support circuitry to coordinate the access of each cell, along with the need to periodically refresh that cell. The faster access time of SRAMs allow their use as the primary cache of the execution unit, whereas DRAMs are generally used as the main semiconductor memory. SRAMs are, therefore, placed on the same address and data bus as the execution unit, whereas DRAMs are linked to the execution unit by a memory controller and stand-alone memory bus.
In addition to having a memory controller between the array of storage cells (DRAMs) and the execution unit, the DRAMs themselves take on numerous forms: fast page DRAMs, extended data out DRAMs, burst extended data out DRAMs, and the more recent synchronous DRAMs (SDRAMs). SDRAMs take advantage of the fact that memory accesses by the execution unit are typically sequential. SDRAMs are thereby designed to fetch all bits within a particular burst in sequential fashion by allowing the column address to be incremented sequentially and in sync with the system clock of the execution unit or processor.
With the increased access speed of the SDRAM came yet another enhancement to DRAMs in general. Instead of providing source-synchronous data capture at the clock frequency, double data rate (DDR) DRAMs allow data to be captured at twice the rate of the clock frequency. Instead of capturing data once per cycle as in single data rate (SDR) DRAMs, DDR DRAMs utilize a 2n prefetch architecture to allow data to be captured twice per clock cycle. Details of the difference between SDR and DDR are set forth in “General DDR SDRAM Functionality,” Micron Technology 2001 (herein incorporated by reference).
While both SDR and DDR DRAMs include the same core memory array of cells, the input/output (I/O) interface is considerably different. For example, DDR utilizes a true and complementary pair of clock signals to formulate the triggering rising and falling clock edges, and also utilizes a data strobe signal (DQS) to drive the data signal (DQ) to and from the memory banks.
One benefit of DDR is the higher speed at which data can be read from or written to the storage cells. Unfortunately, however, the increased speed of the I/O interface within the memory controller limits the available selection of available packing techniques. For example, when the data transfer rate exceeds several 100 MHz, relatively high inductance occur on the data signals sent to and from the memory controller. In an attempt to reduce the inductance, the data pins are kept as short as possible and are placed as close to the ground plane as possible. By shortening the data pins or leads extending from the controller and/or DRAMs and placing those pins near the ground plane, the current loop area and the magnetic flux are minimized. As described in “Circuits, Interconnections, and Packaging for VLSI,” 1990, pg. 321 (herein incorporated by reference), packages which incur the poorest lead inductance are dual in-line packages (DIPs) or small outline packages (SOPs) which have approximately 3-50 nH inductance. Packages that have the smallest lead inductance (0.025-1 nH) are those that employ flip-chip technology.
To take full advantage of the higher transfer speeds of DDR, the integrated circuit having the memory controller also has preferably an array of solder bumps arranged on the upper surface of the integrated circuit. The integrated circuit is then flipped over so that the solder bumps are in alignment with solder balls on a single or multi-layer substrate. The “flipped” integrated circuit is then heated along with the substrate, to establish a reflow bond between the integrated circuit and the substrate. Flip-chip mounting with collapsible solder balls provides the least parasitic inductance and capacitance, generally less than 1 nH and less than 1 pF. See “Circuits, Interconnections, and Packaging for VLSI,” 1990, pg. 91 (herein incorporated by reference).
While flip-chip mounting techniques enjoy lessened parasitic inductance and capacitance, flip-chip mounting is nonetheless relatively expensive. First, the integrated circuit must be laid out with bonding pads on an upper surface, and one or more ground planes either on the integrated circuit near the solder bumps or on the substrate near the solder balls. Second, the added multi-layer substrate and the added encapsulate process needed to secure the collapsible solder balls increases the overall complexity of the packaged integrated circuit. Third, in addition to the specially configured array of solder bumps and the encapsulate between the collapsible solder balls and solder bumps, flip-chip mounting also requires additional mounting of the substrate-connected integrated circuit to a much larger printed circuit board (PCB).
Instead of requiring a special purpose multi-layer substrate, and flip-chip arrangement of solder balls and bumps, it would be desirable to utilize a less expensive packaging technique. For example, use of a lead frame and wire bonds to form a packaged integrated circuit, and simply mounting the leads onto a PCB without any intervening special-purpose substrate would not only be faster, but less costly to implement than flip-chip mounting. However, if conventional lead frames and wire bonding packages are to be used, it would be desirable to implement modifications to the overall data rate transfer of a DDR DRAM.
In addition to reducing the overall packaging costs of the integrated circuit, additional cost savings must be implemented on the PCB to further reduce costs of the interconnect solution. For example, it would be desirable to introduce DDR transfers in a lower cost small outline package (SOP), with a minimum number of layers formed on the PCB. The desired solution would achieve the benefits of DDR, yet also reduce the costs of packaging, interconnect, and PCB complexity that currently exists in the flip-chip mounting solution.